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iC-MG
preliminary
Rev C1, Page 1/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
FEATURES o Real-time tracking, no-missing-code interpolation to 200 kHz input frequency (up to x5, to 20 kHz for x50) o Selectable interpol. factors: x1, x2, x4, x5, x10, x20, x25, x50 o Excellent accuracy (typ. 0.6 LSB) and repeatability (typ. 0.1 LSB) o Differential PGA inputs with selectable input resistance for voltage and current signals o Adjustable signal conditioning for offset, amplitude, phase o Unique signal and calibration stabilization feature: supply of encoder LED or MR bridge via controlled 40 mA current source o Fail-safe RS422 encoder quadrature outputs with index signal o Adjustable index position and length (from 1/4 to 1 T) o Preselectable minimum phase distance supports fail-safe counting o Clipping, loss-of-signal and loss-of-tracking indication o Setup via serial EEPROM interface o Sub-system power switch offers reverse polarity protection for the overall system o Single 5 V supply, operation from -25(40) C to +100(125) C
APPLICATIONS o Optical and magnetic position sensors o Rotary encoders o Linear encoders
PACKAGES
TSSOP20
BLOCK DIAGRAM
VDDS PCOS
+
GNDS VDD
-
iC-MG
COS
COUNTER
REVERSE POLARITY PROTECTION
GND
-
B
NCOS
+
NB
COSINE INPUT / CH.2
SIN
PSIN
A
+
PHASE CORRECTION TAN
-
NA
Z
-
NSIN
+
NZ Sin/D CONVERSION RS422 LINE DRIVER
SINE INPUT / CH1 PZERO
+
SDA SIGNAL LEVEL CONTROLLER E2PROM INTERFACE ZIn PWR NERR INDEX ENABLE SIGNAL MONITOR
-
SCL
-
NZERO
+
ZERO INPUT / CH0
Copyright (c) 2008 iC-Haus
http://www.ichaus.com
iC-MG
preliminary
Rev C1, Page 2/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
DESCRIPTION Interpolator iC-MG is a non-linear A/D converter which, by applying a count-safe vector principle, digitizes sine/cosine sensor signals with selectable resolution and hysteresis. The angle value is output incrementally via differential RS422 drivers as an encoder quadrature signal with an index pulse. The minimum phase distance can be preselected, thus generating fail-safe counter signals and enhancing the noise immunity of the sensor system. Programmable instrumentation amplifiers with selectable gain levels permit differential (in VDIFF or IDIFF mode) or single-ended input signals (in VREF or IREF mode). The modes of operation differentiate between high impedance (V modes) and low impedance (I modes). This adaptation of the iC to voltage or current signals enables MR sensor bridges or photosensors to be directly connected up to the device. The integrated signal conditioning unit allows signal amplitudes and offset voltages to be calibrated and also any phase error between the sine and cosine signals to be corrected. For the purpose of signal stabilization (to minimize the effects of temperature and aging), the conditioned signals are fed into the power supply controller which drives the transmitting LED of optical systems via the integrated 40 mA driver stage (output PWR). If MR sensors are connected this driver stage also powers the measuring bridges. If the control thresholds are reached this is signaled at alarm message output NERR (signal loss due to wire breakage, short circuiting, dirt or aging, for example). iC-MG is protected against a reversed power supply voltage; the integrated supply switch for loads of up to 20 mA extends this protection to cover the overall system. The device is configured via an external EEPROM.
PACKAGES PIN CONFIGURATION TSSOP20 PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PZERO NZERO NSIN PSIN VDDS GNDS PCOS NCOS PWR SDA SCL NB B NA A GND VDD NZ Z NERR Input Zero Signal + Input Zero Signal Input Sine Signal Input Sine Signal + Subsystem Positive Supply Output Subsystem Ground Output Input Cosine Signal + Input Cosine Signal Controlled Power Supply Output (HighSide) Serial E2PROM Interface, data line Serial E2PROM Interface, clock line Incremental Output BIncremental Output B+ Incremental Output AIncremental Output A+ Ground +4.3 ... 5.5 V Supply Voltage Incremental Index Output ZIncremental Index Output Z+ Alarm Message and Test Signal Output (e.g. index enable signal Zin)
iC-MG
preliminary
Rev C1, Page 3/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed. Item No. Symbol Parameter Voltage at VDD, A, NA, B, NB, Z, NZ, SCL, SDA, PWR Voltage at NERR Voltage Pin vs. Pin Voltage at PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, SCL, SDA Current in VDD Current in VDDS, GNDS Current in PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, SCL, SDA, NERR Current in A, NA, B, NB, Z, NZ Current in PWR ESD Susceptibility at all pins Operating Junction Temperature Storage Temperature Range HBM, 100 pF discharged through 1.5 k -40 -40 -0.3 -20 -50 -20 -100 -100 Conditions Min. -6 -6 Max. 6 8 6 VDDS +0.3 400 50 20 100 20 2 150 150 V V V V V mA mA mA mA mA kV C C Unit
G001 V() G002 V() G003 V() G004 V() G005 I(VDD) G006 I() G007 I() G008 I() G009 I(PWR) G010 Vd() G011 Tj G012 Ts
THERMAL DATA
Item No. T01 Symbol Ta Parameter Operating Ambient Temperature Range (extended temperature range of -40 to 125 C on request) Conditions Min. -25 Typ. Max. 100 C Unit
All voltages are referenced to ground unless otherwise stated. All currents into the device pins are positive; all currents out of the device pins are negative.
iC-MG
preliminary
Rev C1, Page 4/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.5...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise noted. Item No. 001 002 003 004 005 006 007 Symbol Parameter Conditions Min. V(VDD) I(VDD) I(VDDS) VDDon VDDoff VDDhys Vc()hi Permissible Supply Voltage Supply Current in VDD Permissible VDDS Load Current Turn-on Threshold VDD Turn-off Threshold VDD Turn-on Threshold Hysteresis Clamp Voltage hi at inputs PSIN, NSIN, PCOS, NCOS, PZERO, NZERO, SCL, SDA Clamp Voltage hi at all pins Clamp Voltage lo at all pins -1.2 0.75 0 -300 10 -10 70 100 0.15 No load, nominal values following Table 10 RSC(3), RZ(3) = 0, GRx = 0x0, GFx = 0x00 RSC(3), RZ(3) = 0, GRx = 0x7, GFx = max. 90 100 2 100 1.015 1.06 1.06 -1 39 1 255 LSB % 110 Tj = -40...125 C, no load Tj = 27 C, no load -20 3.6 3.0 0.4 0.3 1.2 4.0 3.5 4.5 12 0 4.3 3.8 Typ. Max. 5.5 25 V mA mA mA V V V V Unit
General
008 009
Vc()hi VC()lo
11 -0.3 VDDS 1.5 VDDS -10 300 10 130
V V V V A A A % %/K %
Inputs and Signal Conditioning: PSIN, NSIN, PCOS, NCOS, PZERO, NZERO 101 Vin()sig Permissible Input Voltage Range RSC, RZ = 0x1 RSC, RZ = 0x9 102 103 104 105 106 107 108 Iin()sig Iin() Rin() TCRin() VREFin() G G-LSB Permissible Input Current Range RSC(0), RZ(0) = 0, BIASSC = 0 RSC(0), RZ(0) = 0, BIASSC = 1 Input Current Input Resistance vs. VREFin() Input Resistance Temperature Coefficient Input Reference Voltage Gain Factor (Coarse x Fine) RSC, RZ = 0x1 Nominal values following Table 9
Least Significant Gain Factor Cal. Sine channel Cosine channel Step Zero channel Integral Non-Linearity of Gain Factor Cal. S/C-Chan. Gain Ratio Calibration GFC = 0x10, GFS = 0x00...0xFF Range Recommended Diff. Input Signal Vin()diff = V(PCHx) - V(NCHx); RSC, RZ = 0x9 Level RSC, RZ = 0x9 Input Offset Voltage Referenced to side of input pins Referenced to source VOSSC; ORS, ORC = 00 ORS, ORC = 01 ORS, ORC = 10 ORS, ORC = 11
109 110 111
G-INL GR-CR Vin()diff
10 40 25 100 200 600 1200 0.79 3.2 -5 20 0.63 -0.8 200
500 2000
mVpp mVpp V %V() %V() %V() %V() % %
112 113
Vin()os
OFS/C-CR S/C Offset Calibration Range
114 115 116 117 118 119 120
OFS/CLSB OFZ-LSB OFx-INL PH-CR PH-LSB PH-INL fin()max
Least Significant S/C-Offset Cal. Referenced to source VOSSC; ORS, ORC= 00 Step Least Significant Z-Offset Cal. Step Integral Non-Linearity of Offset Cal. S/C Phase Calibration Range Least Significant S/C Phase Cal. Step Integral Non-Linearity of S/C Phase Cal. Permissible Max. Inp. Frequency Referenced to VOSZ; ORZ = 00
5
LSB
0.8
kHz
iC-MG
preliminary
Rev C1, Page 5/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.5...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise noted. Item No. 201 202 203 501 502 503 504 505 506 Symbol Parameter Conditions Min. AAabs AArel AAR Vs()hi Vs()lo Isc()hi Isc()lo Ilk()tri tr() Absolute Angle Accuracy (follow- Referred to 360 deg input signal, ideal and ing calibration) quasi-stable input signals, SELHYS = 0 Relative Angle Accuracy Absolute Angle Repeatability Saturation Voltage hi Saturation Voltage lo Short-Circuit Current hi Short-Circuit Current lo Tristate Leakage Current Rise Time hi TRIHL(1:0) = 11 RL = 100 to GNDS; SSR(1:0) = 01 SSR(1:0) = 10 RL = 100 to VDD; SSR(1:0) = 01 SSR(1:0) = 10 With calibration modes With calibration modes -3 5 20 5 30 2.5 Referred to A/B output period, ideal and quasistable input signals See 201; VDD = const., Tj = const. Vs() = VDD - V(); I() = -20 mA I() = 20 mA -60 20 -40 40 20 -10 0.2 400 400 -20 60 100 40 140 40 140 4 3 100 referred to nominal value Vs() = VDD - V(); ADJ(8:0) = 0x19F, I() = -5 mA ADJ(8:0) = 0x1BF, I() = -10 mA ADJ(8:0) = 0x1DF, I() = -25 mA ADJ(8:0) = 0x1FF, I() = -40 mA V(PWR) = 0...VDD - 1 V; ADJ(8:0) = 0x19F ADJ(8:0) = 0x1BF ADJ(8:0) = 0x1DF V(PWR) = 0...VDD - 1.2 V; ADJ(8:0) = 0x1FF -10 -20 -50 -100 1.2 45 450 CFGIBN = 0x0 CFGIBN = 0xF calibrated at Ta = 25 C 110 180 200 370 220 1.25 50 500 -25 +25 Typ. 1 Max. 2 +10 % mV mV mA mA A ns ns ns ns k A A % Unit
Sine-to-Digital Conversion
Output Line Drivers: A, NA, B, NB, Z, NZ
507
tf()
Rise Time lo
508 509 510 511
Ri()cal I()cal IIk() MTD()
Source Impedance Permissible Load Current Leakage Current with Reversed Supply Voltage Min. Phase Distance Tolerance
Controlled Power Supply: PWR 601 Vs()hi Saturation Voltage hi
1 1 1 1.2 -4 -8 -20 -40 1.3 55 550
V V V V mA mA mA mA V %VDDS mV A A A
602
Isc()hi
Short-Circuit Current hi
Bias Current Source and Reference Voltages 801 802 803 804 VBG VPAH VOSref IBN Bandgap Reference Voltage Reference Voltage Source S/C a. Z Offset Cal. Reference Voltage Source Bias Current Source
iC-MG
preliminary
Rev C1, Page 6/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.5...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise noted. Item No. B01 B02 B03 B04 B05 B06 B07 Symbol Parameter Conditions Min. Vs()lo Isc()lo Ipu() VTMon VTMoff VTMhys Saturation Voltage lo Short-Circuit Current lo Pull-Up Current Source Setup Preparation Threshold Setup Trigger Threshold Versus GND; I() = 4 mA Versus GND; V(NERR) VDD V(NERR) > VTMon V() = 0...VDD - 1 V; EPU = 1 Increasing voltage at NERR Decreasing voltage at NERR VDD + 0.5 0.15 -25 0.3 +25 250 250 -1 0 4 -400 5 2 -300 Typ. Max. 0.4 7 -200 VDD +2 V mA mA A V V V V % mV mV mA Unit
Alarm Message Output: NERR
Setup Trigger Threshold Hystere- VTMhys = VTMon - VTMoff sis
dt(NERR)lo Alarm Indication Time Tolerance Nominal time see table 40 Saturation Voltage VDDS vs. VDD Saturation Voltage GNDS vs. GNS Supply Current in VDD with Reverse Polarity Saturation Voltage lo Short-Circuit Current lo Input Threshold Voltage hi Input Threshold Voltage lo Input Threshold Hysteresis Input Pull-Up Current Input Pull-Up Voltage Clock Frequency SCL Configuration Sequence Shutdown Temperature Shutdown Temperature Hysteresis Single reading sequence Vt()hys = Vt()hi - Vt()lo V() = 0...VDDS - 1 V V() = VDDS - V(); I() = -5 A I() = 4 mA Vs() = VDD - V(VDSS); I(VDDS) = -20 mA Vs() = V(GNDS) - GND; I(GNDS) = 20 mA
Supply Switch and Reverse Polarity Protection: VDDS, GNDS C01 Vs() C02 Vs() C03 I(VDD)rev
Serial EEPROM Interface: SDA, SCL D01 Vs()lo D02 Isc() D03 Vt()hi D04 Vt()lo D05 Vt()hys D06 Ipu() D07 Vpu() D08 f(SCL) D09 tbusy()cfg E01 E02 Toff Thys 400 4 0.8 300 -600 60 500 -300 80 18 155 30 -60 0.4 100 24 75 2 mV mA V V mV A V kHz ms C C
Temperature Monitoring
iC-MG
preliminary
Rev C1, Page 7/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
DEVICE SETUP Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 8 Serial EEPROM Interface . . . . . . . . . . . . . . . . . . Page 10 DEVID: Device ID of the EEPROM providing the chip configuration data (e.g. 0x50) CHKSUM: CRC of chip configuration data (address range 0x00 to 0x2E) Bias Current Source . . . . . . . . . . . . . . . . . . . . . . . Page 11 CFGIBN: Bias Trimming Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 11 MODE: Mode select Input Configurations . . . . . . . . . . . . . . . . . . . . . . Page 12 INMODE: Diff./Single-Ended Input Signal Mode RSC: I/V Mode and Input Resistance, S/C Channel BIASSC: Bias Voltage, S/C Channel RZ: I/V Mode and Input Resistance, Z Channel BIASZ: Bias Voltage, Z Channel S/C Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 13 GRSC: S/C Channel Gain Range GFS: Gain Factor Sine GFC: Gain Factor Cosine ORS: Offset Range Sine ORC: Offset Range Cosine OFS: Offset Factor Sine OFC: Offset Factor Cosine VOSSC: S/C Channel Offset Reference Source VDCS: Intermediate Voltage Sine VDCC: Intermediate Voltage Cosine PHSC: S/C Channel Phase Correction Controlled Power Supply . . . . . . . . . . . . . . . . . . Page 16 ADJ: PWR output adjustment Z Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 GRZ: Z Channel Gain Range GFZ: Gain Factor Zero ORZ: Offset Range Zero OFZ: Offset Factor Zero VOSZ: Z Channel Offset Reference Source Zero Signal Setup . . . . . . . . . . . . . . . . . . . . . . . . . .Page 17 CFGZ: Zero Signal Logic CFGZPOS: Zero Signal Positioning Sine-to-Digital Conversion . . . . . . . . . . . . . . . . Page 16 SELRES: Resolution SELHYS: Hysteresis Output Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17 MTD: Minimum Phase Distance SSR: Slew Rate TRIHL: Drive Mode Error Monitoring and Alarm Output . . . . . . . Page 18 EMTD: Minimal Alarm Indication Time EPH: Alarm Output Logic EPU: Alarm Output Pull-Up Enable EMASKA: Error Event Mask for Alarm Indication EMASKO: Error Event Mask for Driver Shutdown
iC-MG
preliminary
Rev C1, Page 8/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Register Map Adr
0x00
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3 DEVID(6:0)
Bit 2
Bit 1
Bit 0
Serial EEPROM Interface Bias Current Source
0x01
CFGIBN(3:0)
0 1 1 0
0
0
0
0
Operating Modes
0x02
MODE(3:0)
0 INMODE 1 1
Input Configurations
0x03 0 0 0 0
S/C Signal Path, Input Configuration
0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0 1 0 0 VDCS(0) 0 0 0
GFC(4:0) GFS(3:0)
0 0 0
GRSC(2:0)
0 0 0 0 0
GFS(6:4) VDCS(5:1)
0
ORS(0) OFS(3:0)
VDCC(5:0)
0 0 0
ORS(1) 0
ORC(1:0) OFC(6:0)
0 0 1 0 1 0
OFS(7:4)
0 OFC(7)
PHSC(2:0)
0 BIASSC
VOSSC(1:0)
0 0 1 0
PHSC(5:3) RSC(3:0)
0 0
Controlled Power Supply
0x0F 0x10 ADJ(0) 0
ADJ(8:1) GFZ(4:0) OFZ(5:0) VOSZ(1:0) EMASKA(7:0) EMTD(2:0) EMASKO(7:0)
0 0 0 0 0 0
Z Signal Path, Input Configuration
0x11 0x12 0x13 0 BIASZ
GRZ(2:0) ORZ(1:0) RZ(3:0)
Error Monitoring
0x14 0x15 0x16 0x17 0x18 0 0 0 0 1 0 EPH EPU 0
EMASKA(9:8) EMASKO(9:8)
0 0
Zero Signal Setup
0x19 0x1A 0 0 0 0
CFGZ(3:0)
CFGZPOS(7:0) SELRES(7:0) SELRES(14:8) MTD(3:0)
0 0 1 0
Sine-to-Digital Conversion, Minimum Phase Distance
0x1B 0x1C 0x1D 0
SELHYS(3:0) SSR(1:0) TRIHL(1:0)
Output Settings
0x1E
iC-MG
preliminary
Rev C1, Page 9/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Register Map Adr
0x1F 0x20
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved Memory Section 1
Internal use only; keep all bits at zero for initialization Internal use only; keep all bits at zero for initialization
0 0 0 0 1 0 0 0
Reserved Memory Section 2
0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E
Internal use only; keep all bits at zero for initialization Internal use only; keep all bits at zero for initialization Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data Application-specific OEM data CHKSUM(7:0) Internal use only; keep all bits at zero for initialization Internal use only; keep all bits at zero for initialization Internal use only; keep all bits at zero for initialization Internal use only; keep all bits at zero for initialization All 0 and 1 entries are mandatory for device initialization Table 4: Register Map
CRC Data
0x2F
Reserved Memory Section 3
0x30 0x31 0x32 0x33 Notes
iC-MG
preliminary
Rev C1, Page 10/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
SERIAL EEPROM INTERFACE The serial configuration interface consists of the two pins SCL and SDA and enables read access to a serial EEPROM (requirements: 1 Kbit, 128x8, 3.3 V to 5 V operation, device address 0x50 "1010 000"; recommended: Atmel AT24C01B; notes: devices ignoring A2...0 address bit settings are not suitable). Once the supply has been switched on (power down reset) iC-MG reads the configuration from the EEPROM which has the device ID 0x50. Bit errors in the 0x00 to 0x2F memory area are monitored by the CRC deposited in register CHKSUM (see program example; the polynomial used is "1 0001 1101"). Should an error occur while the data is being read in the readin process is repeated; the system aborts following a fourth faulty attempt and tristates the output drivers. As an alternative to the power down reset iC-MG can be triggered to again read in the configuration via pin NERR. To this end pin voltage V(NERR) must initially exceed threshold voltage VTMon (see Electrical Characteristics). Once the pin voltage has dropped to below VTMon iC-MG starts communicating with the EEPROM. The device ID stored in register DEVID is used to address the EEPROM. Example of CRC Calculation Routine
unsigned char ucDataStream = 0 ; i n t iCRCPoly = 0x11D ; unsigned char ucCRC=0; int i = 0; ucCRC = 1 ; / / s t a r t v a l u e ! ! ! f o r ( iReg = 0 ; iReg <47; iReg ++) { ucDataStream = ucGetValue ( iReg ) ; f o r ( i =0; i <=7; i ++) { i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) ) ucCRC = (ucCRC << 1 ) ^ iCRCPoly ; else ucCRC = (ucCRC << 1 ) ; ucDataStream = ucDataStream << 1 ; } }
iC-MG
preliminary
Rev C1, Page 11/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
OPERATING MODES
MODE Code 0x00 0x01 0x02 0x0B Adr 0x02, bit 3:0 Operating Mode ABZ Mode Calibration Mode 1 Calibration Mode 2 System Test Mode * PCH-S A4 Pin A A Pin NA NA VREFIZ NCH-S A8 Pin B B VREFISC PCH-C B4 Pin NB NB IBN NCH-C B8 Pin Z Z PCH-Z VDCS ZIn Pin NZ NZ NCH-Z VDCC NERR NERR NERR
* Note: Setting SELRES=0x132 and SELHYS=0xF is mandatory.
Table 5: Operating Modes iC-MG has several modes of operation which are set via MODE. In addition to the primary operational mode ABZ Mode for the output of encoder quadrature signals via differential line drivers both analog and digital calibration signals can be selected which can be used to set up the integrated signal conditioning unit. ABZ Mode In ABZ Mode complementary signals are always output. Here, converter setting SELRES determines the A/B pulse count and zero signal settings CFGZ and CFGPOS the width and position of the generated zero signal (dependent on an enable from ZIn ). Calibration Mode 1, Mode 2 So that signal amplitudes and offset voltages can be calibrated internal analog signals are switched to the output pins directly and the digital line drivers shut down. Due to internal resistances of up to 4 k a highimpedance measurement is advisable. In Calibration Mode 1 bias current source IBN and the internal zero signal are available after the input amplifier (signals PCH-Z and NCH-Z). The calibration of IBN is described on page 11, that of the zero signal on page 15. In Calibration Mode 2 the conditioned sine and cosine signals are output (signals PCH-S, NCH-S, PCH-C and NCH-C). Additionally, the intermediate potentials of both input channels are also available, with VDCS for the sine and VDCC for the cosine channel. The calibration of these intermediate voltages is described on page 14. System Test Mode System Test Mode permits the fine adjustment of the sine and cosine input signals using digital signals. The registers mentioned above must also be set for this mode. The A4 duty cycle acts as a measure for the offset of the sine channel, with the B4 duty cycle a measure for that of the cosine channel. The duty cycle at A8 represents the phase error between sine and cosine or any deviation from the ideal value of 90. The calibration of differing signal amplitudes enables the duty cycle at B8 . A duty cycle of 50 % is the calibration target for all digital test signals. Signal ZIn is the unmasked digitized zero signal.
BIAS CURRENT SOURCE CALIBRATION The calibration of the bias current source is prerequisite for adherence to the given electrical characteristics and also instrumental in the determination of the chip timing (e.g. the minimum phase distance and SCL clock frequency). For setup purposes Calibration Mode 1 is activated and the IBN current measured using a 10 k resistor switched to VDDS. The setpoint is 200 A which is equivalent to a measurement voltage of 2 V.
CFGIBN Code k 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Adr 0x01, bit 7:4 IBN 79 % 81 % 84 % 86 % 88 % 91 % 94 % 97 %
31 39-k
Code k 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF
IBN 100 % 103 % 107 % 111 % 115 % 119 % 124 % 129 %
31 39-k
Table 6: Bias Current Source Calibration
iC-MG
preliminary
Rev C1, Page 12/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
INPUT CONFIGURATIONS
Figure 1: Input instrumentation amplifier and signal conditioning All input stages are configured as instrumentation amplifiers and thus directly suitable for differential input signals. Referenced input signals can be processed as required; in Single-Ended Input Mode the NZERO input acts as a reference, replacing the input signals from NSIN and NCOS.
INMODE 0 1 Note Adr 0x03, bit 2 Differential input signals Single-ended input signals * * Input NZERO is reference for all inputs.
125 mV and 250 mV (verifiable in Calibration Mode 2). In V Mode an optional voltage divider can be selected which reduces unacceptably large input amplitudes to ca. 25%. The circuitry is equivalent to the resistor chain in I Mode; the pad wiring resistor is considerably larger here, however.
RSC RZ Code -000 -010 -100 -110 1--1 0--1 Adr 0x0E, bit 3:0 Adr 0x13, bit 3:0 Nominal Rin() Internal Rui() 1.7 k 2.5 k 3.5 k 4.9 k 20 k high impedance 1.6 k 2.3 k 3.2 k 4.6 k 5 k 1 M I/V Mode Current input Current input Current input Current input Voltage input Voltage input
Table 7: Input Signal Mode Both current and voltage signals can be processed as input signals, selected by RSC(0) and RZ(0). In I Mode an input resistor Rin() becomes active at each input pin, converting the current signal into a voltage signal. The input resistance Rin() consists of a pad wiring resistor and resistor Rui() which is linked to the adjustable bias voltage source VREFin(). The following table shows the possible selections, with Rin() giving the typical resulting input resistance (see Electrical Characteristics for tolerances). The input resistor should be set in such a way that intermediate potentials VDCS and VDCC lie between
Table 8: I/V Mode and Input Resistance
BIASSC BIASZ Code 0 1 Adr 0x0E, bit 6 Adr 0x13, bit 6 VREFin() 2.5 V 1.5 V Type of sensor Lowside current sink (I Mode) Highside current source (I Mode)
Table 9: Input Bias Voltage
iC-MG
preliminary
Rev C1, Page 13/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
S/C SIGNAL PATH and CALIBRATION The analog voltage signals needed to calibrate the sine signals can be measured in Calibration Mode 2. The characteristic digital parameters for offset, amplitude and phase errors can be measured in System Test Mode. S/C Gain Settings The gain is set in four stages: 1. The sensor supply tracking is shut down and the constant current source for the PWR output set to a suitable output current (register ADJ; current value close to the later operating point). 2. The coarse gain is selected so that differential signal amplitudes of ca. 1 Vpp are produced internally (signal PCHx vs. NCHx for the sine or cosine channel). 3. Using fine gain factor GFC the cosine signal amplitude is then adjusted to 1 Vpp. 4. The sine signal amplitude can then be calibrated to the cosine signal amplitude via fine gain factor GFS.
GRSC Code 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Adr 0x04, bit 2:0 Range with RSC=0x9 0.5 1.0 1.3 1.7 2.2 2.6 3.3 4.0 Range with RSC=0x9 2.0 4.1 5.3 6.7 8.7 10.5 13.2 16.0
Table 10: S/C-Channel Gain Range
GFC Code 0x00 0x01 ... 0x1F Adr 0x04, bit 7:3 Factor 1.00 1.06 6.25 6.25
GFC 31
Table 11: Gain Factor Cosine
GFS Code 0x00 0x01 ... 0x7F Adr 0x06, bit 2:0, Adr 0x05, bit 7:4 Factor 1.0 1.015 6.25 124 6.53
GFS
Table 12: Gain Factor Sine
iC-MG
preliminary
Rev C1, Page 14/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
S/C Offset Calibration To calibrate the offset the reference source must first be selected using VOSSC. Two fixed voltages and two dependent sources are available for this purpose. The fixed voltage sources should be selected for external sensors which already provide stable, self-regulating signals. For the operation of photosensors in optical encoders, iC-MG tracks changes in offset voltages via the signaldependent source VDC when used in conjunction with the controlled power supply output supplying the encoder LED (pin PWR). The VDC potential automatically tracks higher DC photocurrents. To this end intermediate potentials VDCS and VDCC must be adjusted to a minimal AC ripple using the selectable k factor (this calibration must be repeated when the gain setting is altered). The ideal DC voltage level of 0.25 V to 0.5 V is selected via the input resistor Rui(). The feedback of pin voltage V(PWR) fulfills the same task as source VDC when MR bridge sensors are supplied by the controlled power supply output. In this instance the VDC sources do not need adjusting.
VOSSC Code 0x0 0x1 0x2 0x3 Adr 0x0E, bit 5:4 Type of source 0.05 * V(PWR) 0.5 V 0.25 V VDC (ie. VDCS, VDCC)
The calibration range for the S/C offset is dependent on the selected VOSSC source and is set using ORS and ORC. Both sine and cosine signals are then calibrated using factors OFS and OFC. The calibration target is reached when the DC fraction of the differential signals PCHx versus NCHx is zero.
ORS ORC Code 00 01 10 11 Adr 0x09, bit 0; Adr 0x08, bit 7 Adr 0x0A, bit 5:4 Range x2 x4 x12 x24
Table 15: S/C-Channel Offset Range
OFS OFC Code 0x00 0x01 ... 0x7F Adr 0xA, bit 3:0; Adr 0x9, bit 7:4 Adr 0xC, bit 0; Adr 0xB, bit 7:1 Factor 0 0.0079 ... 1 Code 0x00 0x01 ... 0xFF Factor 0 -0.0079 ... -1
Table 16: S/C-Channel Offset Factors S/C Phase Correction If the phase shift between the sine and cosine signal deviates from the ideal 90 this can be compensated for using parameter PHSC. Following this the calibration of the amplitude compensation, intermediate potentials and offset voltages may have to be corrected.
PHSC Code 0x00 0x01 ... 0x1F Adr 0xD, bit 2:0; Adr 0xC, bit 7:5 Correction angle +0 + 0.63 ... + 20.2 Code 0x20 0x21 ... 0x3F Correction angle -0 - 0.63 ... - 20.2
Table 13: S/C-Channel Offset Reference Source
VDCS VDCC Code 0x00 0x01 ... 0x3F Adr 0x07, bit 4:0; Adr 0x06, bit 7 Adr 0x08, bit 6:1 VDC = k * V (P - In) + (1 - k ) * V (N - In) k = 0.33 k = 0.335 ... k = 0.66
Table 14: S/C-Channel Intermediate Voltages
Table 17: Phase Correction
iC-MG
preliminary
Rev C1, Page 15/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Z SIGNAL PATH and CALIBRATION The analog voltage signals needed to calibrate the zero signal are available in Calibration Mode 1. In addition it is possible to check the phase position of the PZERO/NZERO enable signal in System Test Mode. Gain Settings Parallel to the conditioning process for the S/C signals the zero signal gain is also set step by step: 1. The tracking of the sensor supply is shut down and the constant current source for the PWR output set to a suitable output current (register ADJ; current value close to the later operating point). 2. Coarse gain is selected so that differential signal amplitudes of ca. 1 Vpp are generated internally (signal PCHx vs. NCHx). 3. GFC then permits fine gain adjustment to 1 Vpp.
GRZ Code 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Adr 0x11, bit 2:0 Range with RZ=0x9 0.5 1.0 1.3 1.7 2.2 2.6 3.3 4.0 Range with RZ=0x9 2.0 4.1 5.3 6.7 8.7 10.5 13.2 16.0 OFZ Code 0x00 0x01 ... 0x1F
Offset Calibration To calibrate the offset the source of supply must first be selected using VOSZ (see S/C Offset Calibration for further information). For the zero signal path the signal dependent source is VDCS.
VOSZ Code 0x0 0x1 0x2 0x3 Adr 0x13, bit 5:4 Type of source 0.05 * V(PWR) 0.5 V 0.25 V VDC= VDCS
Table 20: Z-Channel Offset Reference Source
ORZ Code 00 01 10 11 Adr 0x12, bit 1:0 Range x2 x4 x12 x24
Table 21: Z-Channel Offset Range
Adr 0x12, bit 7:2 Factor 0 0.032 ... 1 Code 0x20 0x21 ... 0x3F Factor 0 -0.032 ... -1
Table 18: Z-Channel Gain Range
GFZ Code 0x00 0x01 ... 0x1F Adr 0x11, bit 7:3 Factor 1.00 1.06 6.25 6.25
GFZ 31
Table 22: Z-Channel Offset Factor
Table 19: Z-Channel Gain Factor
iC-MG
preliminary
Rev C1, Page 16/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
SIGNAL LEVEL CONTROLLER Via the controlled power supply (pin PWR) the input signal levels for the sine-to-digital converter can be kept constant regardless of temperature and aging effects by tracking the sensor supply. Alternatively, the PWR output can be used as a constant current source for adjusting the signal conditioning, for example. ADJ(6:0) selects the desired current for the PWR output; when adjusting the signal conditioning ideally amplitudes of ca. 1 Vpp should be possible for the PCHx to NCHx signal.
ADJ (8:7) Code 00 01 10 11 Adr 0x10, bit 7:6 Function Control to sine/cosine square Control to sum of sine/cosine Current source Not permitted ADJ (4:0) Code 0x00 ... 0x1F Note Adr 0x10, bit 3:0; Adr 0x0F, bit 7 Function 3.125 % of Isc(PWR) ... 100 % of Isc(PWR) Settings apply with current source mode.
Table 25: PWR Output Short-Circuit Current
ADJ (4:0) Code 0x00 ... 0x1A ... 0x1F Note Adr 0x10, bit 3:0; Adr 0x0F, bit 7 Function 60% ... ca. 100% ... 120% Settings apply with s/c square control mode. Recommended entry for 1.0 V is 0x1A.
Table 23: PWR Output Operating Mode
ADJ (6:5) Code 00 01 10 11 Adr 0x10, bit 5:4 Function 5 mA range 10 mA range 25 mA range 50 mA range
Table 26: PWR Output Signal Adjustment
ADJ (4:0) Code 0x00 ... 0x1F Note Adr 0x10, bit 3:0; Adr 0x0F, bit 7 Function VDCS + VDCC = 224 mV ... VDCS + VDCC = 472 mV Settings apply with sum control mode.
Table 24: PWR Output Current Source Range
Table 27: PWR Output Signal Adjustment
SINE-TO-DIGITAL CONVERSION
SELRES Code 0x00E0 0x01B0 0x0398 0x0414 0x090a 0x1305 0x1804 0x3102 Adr 0x1C, bit 6:0; Adr 0x1B, bit 7:0 Angle Steps (per period) 4 8 16 20 40 80 100 200 Interpolation Factor x1 x2 x4 x5 x10 x20 x25 x50 Permiss. Input Frequency 200 kHz 200 kHz 200 kHz 200 kHz 100 kHz 50 kHz 40 kHz 20 kHz SELHYS Code 0x0 to 0x1 0x2 0x3 to 0xD 0xE 0xF* Note Adr 0x1D, bit 3:0 Function Device test only 1 increment ( 1.8) 1.5 to 6.5 increments ( 2.7-11.7) SELRES(6:1) increments, i.e. 0.5 LSB SELRES(6:0) increments, i.e. 1 LSB *Not permitted in combination with SELRES=0x00E0
Table 29: Encoding of conversion hysteresis The angle hysteresis is set via SELHYS in multiples of the increment size. With reference to the input sine cycle the maximum length can be 45.
Table 28: Resolution of Sine-to-Digital Conversion
iC-MG
preliminary
Rev C1, Page 17/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
OUTPUT SETTINGS Configuration of Output Drivers The output drivers can be used as push-pull, lowside or highside drivers. TRIHL(1:0) selects the mode of operation. In order to avoid steep edges during transmission via short cables the slew rate can be reduced using SSR (tolerances as given in Electrical Characteristics).
TRIHL Code 00 01 10 11 Adr 0x1E, bit 1:0 Function Push-pull operation Highside driver mode (P channel open drain) Lowside driver mode (N channel open drain) Not permitted
Zero Signal Positioning The output of the zero pulse, generated internally, is based on an enable from ZIn which can be observed in System Test Mode and in ABZ Mode at pin NERR (via EMASKA= 0x010 and EMTD= 0x0). As the offset calibration of the zero signal alters the signal width the correct position and width of signal ZIn should be checked before the digital configuration parameters are determined. The zero pulse output position can be selected via CFGZPOS(6:0); the cycle count begins with the sine zero crossing. No zero pulse is output for all values which are either greater than or equal to the interpolation factor.
CFGZPOS Adr 0x1A, bit 7:0 Function Enables the selection below Count of A/B period releasing the Z output
Table 30: Output Drive Mode
SSR Code 01 10 Note Adr 0x1E, bit 3:2 Function Nominal value 25 ns Nominal value 80 ns Entries 00 and 11 are not permitted Bit 7 6:0
Table 33: Zero Signal Positioning
CFGZ Code 1000 0100 0010 0001 Adr 0x19, bit 3:0 Function Enables Z= 1 with A= 1, B= 1 Enables Z= 1 with A= 1, B= 0 Enables Z= 1 with A= 0, B= 0 Enables Z= 1 with A= 0, B= 1
Table 31: Output Slew Rate Minimum Phase Distance The minimum phase distance for the A/B and Z output signals can be preselected using MTD(3:0). This setting limits the maximum possible output frequency for secure transmission to counters which are either unable to debounce noise spikes or only permit low input frequencies.
MTD Code 0x8 0x9 ... 0xE 0xF Note Adr 0x1D, bit 7:4 Function 200 ns 400 ns ... 1.4 s 1.6 s Codes 0x0 to 0x7 are not permitted. All timing specifications are nominal values, see Elec. Char. No. 511 for tolerances.
Table 34: Zero Signal Logic
Table 32: Minimum Phase Distance When selecting the minimum phase distance the slew rate setting of the RS422 output drivers and the length of cable used must be taken into consideration. Figure 2: Zero signal logic options (example for CFGZPOS(7)=1, CFGZPOS(6:0)=0x6)
iC-MG
preliminary
Rev C1, Page 18/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
ERROR MONITORING and ALARM OUTPUT iC-MG monitors input signals, the internal interpolator and the controlled sensor supply via which the input signal levels are stabilized. Should the sensor supply tracking reach control limits this can be interpreted as an end-of-life message, for example. Two separate error masks determine whether error events cause the RS422 output drivers to shutdown (mask EMASKO) or are signaled as an alarm via the current-limited open drain I/O pin NERR (mask EMASKA).
EMASKO Bit 9 8 7 6 5 4 3 2 1 0 Adr 0x17, bit 1:0; Adr 0x16, bit 7:0 Error event n/a Temporal tracking error (e.g. after cycling power) Loss of tracking due to excessive input frequency n/a Excessive temperature shutdown System error: I/O pin NERR pulled to low by an external error signal (only permitted with EPH = 0) PWR control out of range (at max. limit) PWR control out of range (at min. limit) Signal clipping (excessive input level) Loss of signal (poor input level or s/c phase out of range)
The display logic and minimum indication time are settable; an internal pull-up current source can be switched in. At the same time pin NERR has an input function to trigger a new configuration run (see Serial EEPROM Interface).
EPU Code 0 1 Adr 0x17, bit 2 Function No internal pull-up active Internal 300 A pull-up source active
Table 37: Alarm Output Pull-Up Enable
EPH Code 0 1 Adr 0x15, bit 2 Pin logic Low on error (otherwise Z) Z on error (otherwise low)
Table 38: Alarm Output Logic
EMTD Code 0x0 0x1 0x2 0x3 Adr 0x15, bit 5:3 Indication time 0 ms 12.5 ms 25 ms 37.5 ms Code 0x4 0x5 0x6 0x7 Indication time 50 ms 62.5 ms 75 ms 87.5 ms
Table 35: Driver Shutdown Error Codes Table 39: Minimal Alarm Indication Time
EMASKA Bit 9 8 7 6 5 4 3 2 1 0 Adr 0x15, bit 1:0; Adr 0x14, bit 7:0 Error event n/a Temporal tracking error (e.g. after cycling power) Loss of tracking due to excessive input frequency n/a Excessive temperature warning Ungated index enable signal Zin PWR control out of range (at max. limit) PWR control out of range (at min. limit) Signal clipping (excessive input level) Loss of signal (poor input level or s/c phase out of range)
Table 36: Alarm Output Error Codes
iC-MG
preliminary
Rev C1, Page 19/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
iC-MG
preliminary
Rev C1, Page 20/20
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
ORDERING INFORMATION
Type iC-MG Evaluation Board
Package TSSOP20
Order Designation iC-MG TSSOP20 iC-MG EVAL MG1D
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.de/support_distributors.php

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